The present invention relates to electronic memory devices and, more particularly, to a device having an improved cell structure, cell array, and methods of operation of a semiconductor memory.
MOS (metal oxide semiconductor) transistor technology was developed and became practical few decades ago, several types of memory devices were introduced since that time among them are UVEPROMs, full-featured EEPROMs, Flash-EEPROMs, Analog Storage EEPROMs, volatile DRAMs, non-volatile DRAMs, volatile SRAMs, non-volatile SRAMs, Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), Artificial Neural Network (ANN) devices, and other customized memory devices.
Volatile SRAM is a static read/write random access memory whose storage cells are remain in a given state until the information is intentionally changed, or the power to the memory circuit is cut off.
Volatile dynamic random access memories (DRAMs) is likewise a semiconductor memory that stores binary information. The word xe2x80x9cdynamicxe2x80x9d refers to the fact that the charge representing the stored information is refreshed or replenished. Typically the information stored in the capacitor of each memory cell is either a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d representing one digital bit per one physical memory cell. Later this data may be read out from the memory cell of the device. The most commonly used DRAM chip is a read/write random access memory which is based on a memory cell that is structures to include one transistor one capacitor combination, in which the digital information is represented by charges that are stored in the storage capacitor. The storage capacitor has one of its plates acting as a storage node and the other plate acting as a plate that is connected to adjacent memory cell capacitors and is biased at some voltage. When the memory cell is not-selected (also referred to below as deselected) the memory cell transistor is turned off and disconnects the storage plate of the capacitor from any voltage or current source and the storage plate of the DRAM""s capacitor is said to be floating.
In a dynamic random access memory or DRAM the information is refreshed or rewritten as needed to avoid losing information because of electrical activity and read/write operations in the memory array including operations associated with neighboring memory cells. In this way a high or xe2x80x9c1xe2x80x9d logical level signal is restored to a stored xe2x80x9c1.xe2x80x9d The refresh operation occurs by sensing or reading what is stored in a memory cell and restoring it to the proper voltage level that represents the same logical state.
There have been significant advances in the art of memory cells. Many such advances are equally applicable to both EEPROMS and DRAMs, and it should be understood that new or improved element of a cell structure can be of great utility in any semiconductor memory cell. The utility is more noticeable when the memory cell is comprised of fewer elements. For example a DRAM memory cell (either volatile or non-volatile) having a transistor and a capacitor typically uses a MOSFET transistor and a capacitor structure of the same materials that are used in some EEPROMs such as the EEPROMs disclosed in U.S. Pat. Nos. 4,845,538 and 5,166,904 issued to the applicant of this application and are expressly incorporated herein by reference.
Non-Volatile SRAMs (NOVRAMs) were developed in the early 1980""s and include a cell that is comprised of a combination of SRAM cell element and at least a portion of an EEPROM cell element.
Generally the goal in forming any memory device is to minimize the physical size of the memory cell and memory array thereby to maximize the packing density of cells per chip area which results in exponential increase in the production yield of good chips from a semiconductor wafer.
Generally, it is desirable to have the highest value of charge possible stores in the memory cell capacitor, especially since the memory cells are getting smaller in each new generation of DRAMs and EEPROMs. Storing higher value of charge in the capacitor generally leads to more reliable operation, higher immunity to soft errors caused by alpha-particles and higher speed operation due to the improved ratio of cell signal to array noise. To increase the amount of stored charge in the memory cell, either the voltage or the capacitance, or both, must be increased according to the charge equation Q=CV, where Q is the charge value, C is the capacitance value and V is the voltage value. Certain tradeoffs are involved in the method selected to increase the stored charge. If one decides to increase the capacitance of the memory cell, either a larger physical capacitor footprint area is needed which exponentially increases manufacturing cost of the memory chip, or some innovative solution is required (such as disclosed and claimed by the Applicant of the instant application in U.S. Pat. No. 5,166,904) in order to reduce the physical footprint area of the storage node of the capacitor using economically affordable semiconductor chip fabrication processing steps. On the other hand, increasing the voltage on the chip is not desired because it increases the programming time in of the cells in EEPROMs, causes reliability constrains which prevents the use of thin dielectric layers within the memory cell capacitor and under interconnect lines that form the memory array and its associated peripheral circuits and reduces efficiency. It would be greatly advantageous to provide a memory cell with increased capacitance and reduced operating voltages inside the chip.
U.S. Pat. No. 4,763,299 issued to the applicant herein programs by using hot electrons from the substrate. It has a very high programming efficiency. The programming time of a single cell of this embodiment is much shorter than that of a tunneling-program mechanism alone, in the range of one micro second (1 uS). This programming efficiency also reduces the programming drain-source current to about one microampere (1 uA), which is much lower in comparison to other cells that program by use of hot electrons from the substrate. The shorter programming time of the cell of ""299 patent together with the low programming current becomes extremely advantageous in applications such as Solid-State-Disks for computers, hand-held computers, and for IC-Card Cameras in which the digitally processed image is rapidly stored in a EEPROM semiconductor memory which can be produce at lower cost than SRAM memory. It is estimated that the IC-Card Camera will take over the multi-billion dollar photographic market place in the near future. Construction of IC-Cards from memories that are based on chips that are constructed using memory cells that comprise one capacitor-one transistor configuration are much more suitable for use in IC-Cards because of the lower cost afforded by these type of memories as oppose to SRAM based IC-Cards.
It is desired to further reduce the programming/erasure voltage of EEPROM cells, while compensating by increasing the capacitance of the cells, while reducing the cell size in order to reduce production cost. Preferably, the foregoing should be accomplished using conventional photolithography equipment (such as photo-light based step-and-repeat cameras and projection aligners, conventional chemicals and photoresists, etc.)
The memory array of memory chips can be further reduced in size if the arrangements of the memory cells, or groups of memory cells is configured in a novel way and in order to take advantage of certain constrains induced by characteristics of materials and known practical limitations of processing equipment for forming structures such as interconnect wires from those materials. For example it is known that a common interconnect metal in chips is formed of aluminum-silicon-copper, which has a low ohmic sheet resistance per square of below 40 milliohm, however the definition of a minimum line width of interconnect is typically much wider than the line width of polycrystalline silicon interconnect which has ohmic sheet resistance per square of about 30 ohms. This brings about the need to take advantage of this facts in order to further reduce the size of the memory array matrix beyond the size reduction that is contributed by the advantage of the memory cell.
The storage density of information in a memory chip can also be increased beyond the contribution of the advantages of the physical memory cell by storing more than one logical bit per physical memory cell. This is disclosed in some details in U.S. Pat. No. 5,278,785 issued to the applicant of this application and which is incorporated herein by reference. Memory chips or memory systems that use such a storage concept can benefit from improved reliability of the stored data within the physical memory cell and from improved performance of such memory cells.
The invention provides an improved memory cell employing the polysilicon tunneling concept to erase and to program.
The invention provides a smaller memory cell size with an additional polysilicon which is shared between two read control word-lines, the addition of the polisilicon line making the implementation of EEPROM memories using substrate materials other than silicon easier.
The invention provides a cell array and process for production thereof in which four cells share a diffusion terminal and a polysilicon erase terminal that is partially disposed over a diffusion bit line, and each cell""s floating gate is an elongated member that has a programming section and an erase section disposed about the bit-line axis.
The invention provides cell structures pertaining to UVEPROM (ultra-violet erasable and hot electron programmable ROM), One-Time Programmable (OTP) EPROM, Flash-EEPROM, thin tunneling dielectric EEPROMs or DRAMs that use insulated control gate for the memory transistor.
The invention allows better control of the channel length dimension of the floating gate by use of chemical definition, as opposed to a photolithography equipment.
This invention provides other EEPROM cells that use the polysilicon to polysilicon tunneling concept to erase and also to program. The process to fabricate the cell and array is also an improved process to build embodiments of memory cells such as the cell of U.S. Pat. No. 4,763,299 (the ""299 patents), which result in a smaller cell size thus reduce production cost.
One aspect of the invention discloses an operation as an EEPROM with a memory cell size smaller than the cell disclosed in U.S. Pat. No. 4,845,538, due to the use of a new capacitor structure that uses an additional polysilicon line that is used as an upper capacitor plate and that is shared with other memory cells.
Another embodiment of the present split-gate invention pertaining to UVEPROM (ultra-violet erasable and hot electron programmable ROM), One-Time Programmable (OTP) EPROM, Flash-EEPROM, or other EEPROMs that require only one insulated control gate for the memory transistor, improves on the previous art by providing a smaller cell size if the same minimum critical- dimension of photolithography equipment are used in fabrication of the cell. Also it provides better control of the channel length dimension of the floating gate, by using chemical definition, as oppose to a definition by photolithography equipment which depends on the precision of the machinery""s resolution and misalignment, in addition to the photoresist resolution. The embodiment provides by means of self-alignment a better control over the coupling overlap-area between the drain diffusion and the floating gate in order to minimize this coupling while keeping it to a controlled value. This self-alignment together with a uniform capacitive coupling between the floating gates and their associated word-lines independently to the floating gate""s location within the array provide for a more uniform read current and for more uniform programming voltage and timing conditions for all the memory cells and therefore provide for improved manufacturing yield.
Another aspect of the invention provides a structure that reduces the chance that undesirable parasitic electrons will travel to the floating gate of a transistor from its channel area thereby increasing the reliability and reducing the data error problem due to this effect. The structure includes a sandwich of thermal oxide and deposited TEOS oxide as a gate oxide under the floating gate.
Another aspect of the invention provides an improved split-gate non-volatile memory transistor that is suited to store large number of quantized charge level that represent digital bits or analog signal voltage. This is done by forming the gate oxide directly under the control gate, which gate oxide is adjacent the gate oxide of the floating gate, of a sandwich of thermal oxide and deposited TEOS oxide. Thereby reducing the threshold voltage variation among memory cells and among chips of different manufacturing batches.
Another aspect of the invention improves the alignment between the erase gate and the control gate of a memory cell. It also improves the alignment between the erase gate and the erase region of the floating gate. This is accomplished while retaining the thickness of the dielectric layer (for example silicon dioxide) between the floating gate and the control gate uniform. This uniformity is achieved by preventing encroachment of the oxide that is formed after the control gate is formed from encroaching into the area between the control gate and the floating gate. This is done by thermally growing a thin silicon dioxide layer that does not consume much polysilicon material from the two layers and thereafter depositing a silicon dioxide at lower temperature on the thin thermal oxide.
Preventing this encroachment is important because if it occurs it makes thickness of the dielectric near the edges of the control gate thicker than the thickness of the same dielectric near the center of the control gate. This has the negative effect of reducing the coupling capacitance between the control gate and the floating gate and prevents easy scaling down of the transistor.
Another aspect of the invention provides a capacitor structure that increases the capacitance per unit-area of the underlying substrate when the unit-area that is considered is the area that is disposed directly under the bottom plate of the capacitor. The increase in capacitance results from the fact that a surface of the bottom plate that comes in contact with the dielectric material of the capacitor is textures or engraved to form undulations or apserities and thereby increase the effective capacitor area which directly increases the capacitance value of the capacitance. However to reduce charge transport between the plates of the capacitor an insulator that is characterized by exhibiting a bulk-limited type of electron conduction is used as part of the dielectric in order to reduce the possibility of charge transport between the plates. The insulator also has a dielectric constant that is higher than the dielectric constant of a silicon dioxide thereby further increasing the capacitance of the capacitor and thereby further reducing the possibility of charge transport between the plates under the voltage operating conditions across the capacitor plates.
This capacitor structure improves the operation of several type of electrically readable and electrically writable memory cells including volatile DRAM such as a DRAM disclosed in U.S. Pat. No. 4,937,650, issued to Shinriki and is expressly incorporated herein by reference, or a DRAM described in an article titled xe2x80x9cA 1 Mb DRAM with 3-Dimensional Stacked Capacitor Cellsxe2x80x9d, by Y. Takmae, et al., in ISSCC-Digest of Papers, Feb. 15, 1985, pg 250, and is expressly incorporated herein by reference, or a Non-Volatile DRAM and dynamic latch circuits that are used in logic circuits such as D-flip-flops. The capacitor is also fit for use in other electronic circuits such as voltage multipliers and charge pumps that are use for power conversions. The capacitor is also fit for use in analog circuits such as switch-capacitor filter circuits, digital-to-analog (D/A) and analog-to-digital (A/D) circuits, and analog sample-and-hold circuits.
Another aspect of the invention is an architecture for an array of memory cells that uses two select lines in each end of an array segment to allow access to an embedded bit-line diffusion thereby eliminating the need for a physically wide metal wire that connects to and along that embedded bit-line. The isolation between adjacent bit-lines that are embedded is performed by a shield gate which also provide the isolation between adjacent bit-lines that are not embedded. This results in reduction in memory array area per given number of memory cells.
Another aspect of the invention is an architecture for an array of memory cells that uses only one select line in each end of an array segment and another select line that is used to connect between two adjacent array segments along the bit line axis and to allow access to an embedded bit-line diffusion segment that is isolatable and extendable thereby eliminating the need for a physically wide metal line that connects to and along that embedded bit-line. This results in reduction in memory array area per given number of memory cells.